This invention relates to a semiconductor memory device and, in particularly, to a semiconductor memory device including a word line driving circuit for driving a word line which is substituted by a redundancy circuit.
In recent years, a semiconductor element is moved to finer design rules and a semiconductor device is made on a large scale. More specifically, this trend is remarkable in a field of semiconductor memory devices. For example, in a Dynamic Random Access Memory (which is abbreviated as DRAM), a product having a memory capacity of 1 gigabits is developed and goes into actual use.
A large-capacity semiconductor memory device comprises not only a main memory array area where normal memory cell arrays are arranged but also a redundancy memory array area where a spare memory cell arrays are arranged. When a defect is found in a part of the main memory array area, a redundancy circuit substitutes a redundancy memory cell for a defective memory cell. By giving relief to the defective memory cell by the redundancy circuit, yields of a large scale semiconductor memory device are improved and the costs thereof is cut down.
However, the semiconductor memory device with the redundancy circuit gives rise to a problem as follows. When a short failure between a word line and a bit line occurs, a memory cell array in question is substituted by the redundancy circuit. However, in a defective memory cell array in a standby state, the word line has a potential equal to a ground potential VSS and the bit line has a potential equal to a precharge potential VBLP which is higher than the ground potential VSS. Therefore, a constant potential difference steadily keeps on applying to a short area in a standby state and there is a malfunction so as to flow a penetrating current in the short area.
In the manner which will later be described in conjunction with FIGS. 1 through 3, in a case where the word line is not selected in a state where a memory cell is standby, the word line becomes a low level and the bit line and an inverted bit line become the precharge potential. Accordingly, in a case where the short failure occurs between the word line and the bit line, a malfunction current flows from the bit line having the precharge potential to the word line having the low level. The malfunction circuit has a current value of about 25 μA per one short area of the word line and the bit line. For example, in the DRAM of 512 Mbits, there are two short areas of the word line and the bit line per a chip. Accordingly, the malfunction current of about 50 μA flows.
On the other hand, in DRAMs for use in portable devices that are called mobile DRAMs, it is desirable to decrease current consumption because of battery-powered. A consumed current spec of the standby state for low consumed current DRAMs has a dependence on temperature. In a case of the DRAM of 512 Mbits, the consumed current spec is equal to about 200 μm at room temperature of about 45° C. Accordingly, the malfunction current of 50 μA becomes 25% of the consumed current spec. Therefore, if measures are not taken against this, a major problem is created on production because the consumed current spec is over, yields are reduced, and it is unprofitable in cost. It is therefore desirable to reduce the malfunction current in the defective memory cell substituted by the redundancy circuit.
Various prior arts in relation to the redundancy circuit or the redundancy memory cell array are already known. By way of example, a patent document 1 (Japanese Unexamined Patent Publication of Tokkai No. 2002-100,199 or JP-A 2002-100199 which corresponds to U.S. Pat. No. 6,618,300) discloses a technical idea in which a redundant subsidiary word selection circuit is eliminated at every plate. In a semiconductor memory device disclosed in the patent document 1, a plurality of banks are arranged on a semiconductor substrate. A plurality of memory array groups are arranged on the plates. Redundant memory cell groups replace a memory cell array, including a defective memory cell, and are arranged at every plate. Subsidiary word selection circuits switch subsidiary word selection lines at every plate. Each of the subsidiary word selection circuits has a selection unit which selects a subsidiary word selection line on the plate belonging thereto and a redundant subsidiary word selection line of the redundant memory cell array arranged on the other adjacent plate.
Furthermore, a patent document 2 (Japanese Unexamined Patent Publication of Tokkai No. Hei 9-36,328 or JP-A 9-36328 which corresponds to U.S. Pat. No. 5,761,149) discloses a technical idea in which a current leakage is not produced in a stand-by state of the DRAM. In a DRAM disclosed in the patent document 2, the DRAM is provided with a main word line; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which extended so as to perpendicular intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the DRAM, the voltage level of each of the main word line and the subsidiary word selection line is made to equal to the ground potential when the line is in a not-selected state.
A patent document 3 (Japanese Unexamined Patent Publication of Tokkai No. 2000-173,290 or JP-A 2000-173290 which corresponds to U.S. Pat. No. 6,188,620) disclose a selection method of a redundancy word driver and a main word driver. A semiconductor memory device disclosed in the patent document 3 includes the redundancy word driver to select a redundancy memory cell and the main word driver to select a normal memory cell. It is judged on the basis of an address input whether a redundancy memory cell or a main word is selected and thereby a time to drive a word line is shortened. In a redundancy judgment circuit, control signals RDC0 to activate redundancy word drivers and a control signal XDC to activate a main word driver are produced, by using dynamic NOR circuits and a dynamic AND circuit that can each set an initial state of an output signal thereof regardless of an input signal, wherein the control signals RDC and XDC in initial states are respectively set to levels at which the redundancy word drivers and main word driver are all inactive.
A patent document 4 (Japanese Unexamined Patent Publication of Tokkai No. 2000-100,195 or JP-A 2000-100195 which corresponds to U.S. Pat. No. 6,154,399) discloses a semiconductor storage device having a redundancy circuit. The semiconductor storage device disclosed in the patent document 4 can provide an enhanced rate of defective sub-word line replacement by independently controlling the activation and deactivation of redundancy sub-word lines. Redundancy sub-word lines can be connected to different redundancy sub-word drivers. Sub-word selecting circuits can generate 2-bit redundancy sub-word selecting signals from sub-word selecting signals and fuse output signals received from a fuse circuit. Redundancy sub-word selecting signals can independently active and inactive redundancy sub-word lines coupled to redundancy sub-word drivers.
A patent document 5 (Japanese Unexamined Patent Publication of Tokkai No. Hei 3-25,793 or JP-A 3-25793) discloses a semiconductor memory device comprising a memory cell array, means for selecting memory cells in the memory cell array, and a tristate output circuit for outputting readout data. The memory cell array is divided into a plurality of subsidiary memory arrays. One word is divided into a plurality of sub-words. Each of the sub-words is selected by a corresponding to sub-word control signal.
However, the above-mentioned prior art patent documents 1 to 5 neither describe nor understand a problem for the malfunction current in the defective memory cell. Accordingly, inasmuch as the problem is not understood, the above-mentioned prior art patent documents 1 to 5 never teach technique for resolving the problem.